1. Field of the Invention
The present invention relates to a method for correcting erroneous data read from a recording medium such as an optical disk or a magnetic disk, and a disk accessing apparatus which can effect the method.
2. Description of the Related Art
Disk accessing apparatuses, which execute data transfer with recording media such as an optical disk and a magnetic disk, require a fast operational speed. One way of increasing the operational speed of a disk accessing apparatus is to increase the operational speed of a signal processing unit provided in the disk accessing apparatus. To meet this requirement, the signal processing unit includes a first-in first-out (FIFO) type speed matching buffer provided between a disk interface and a data transfer unit.
FIG. 1 is a block diagram of a conventional signal processing unit provided in a disk accessing apparatus for an optical disk. The signal processing unit 50 includes an MPU (Micro Processing Unit) interface unit 51, an internal processor 52, a disk interface 53, a host interface 54, an error correcting unit 55 and a data transfer controller 56, which are connected to one another via an internal control bus 58. The signal processing unit 50 further includes a speed matching buffer 57.
The MPU interface unit 51 exchanges control signals with an MPU (not shown) performing the general system control of the disk accessing apparatus. The internal processor 52 includes a program ROM (Read Only Memory) 52a, and performs the general control of the signal processing unit 50 in accordance with firmware stored in the program ROM 52a. The disk interface 53 is connected to a drive head (not shown) in the disk accessing apparatus. The disk interface 53 receives read data D.sub.R, i.e., signals read from an optical disk by the drive head. From this read D.sub.R, the disk interface 53 reads data in the ID portion in a sector and determines if the sector is the target sector.
FIG. 2 shows the sector format of an optical disk formatted according to the ISO standards (3.5 inches and single-density capacity). Each sector 60 is separated into an ID area 61 and a data area 62. The ID area 61 includes a sector mark field, a plurality of lock-up pattern fields, a plurality of address mark fields, a plurality of physical address fields, a postamble field and an optical offset, which are not shown. The sector mark field is where a sector mark is to be recorded. The lock-up pattern fields are where lock-up patterns are to be recorded. The address mark fields are where addresses are to be recorded. The physical address fields are where physical addresses are to be recorded. The data area 62 includes a plurality of user data fields 62a, a cyclic redundancy check (CRC) field 62b, an error correction code (ECC) field 62c, a sync pattern (SYNC) field 62d, a plurality of resync pattern (RESYNC) fields 62e, a postamble (PA) field 62f and a buffer (BUFF) field 62g. The sync pattern field 62d is provided at the head of the data area 62. The resync pattern fields 62e are provided among the individual fields 62a, 62b and 62c.
FIG. 3 presents the detailed illustration of the user data fields 62a, the cyclic redundancy check fields 62b, the error correction code fields 62c, the sync pattern field 62d, and the resync pattern fields 62e.
The sync pattern field 62d includes three sync patterns SB1, SB2 and SB3. Each of the sync patterns SB1-SB3 consists of one byte. The resync pattern fields 62e include thirty-nine resync patterns RS1 to RS39. Each of the resync patterns RS1-RS39 consists of one byte.
The user data fields 62a each consisting of fifteen bytes are provided between the sync pattern SB3 and the resync pattern RS1 and among the resync patterns RS1-RS34. Groups of fifteen bytes of data D1 to D15, D16 to D30, . . . , and D496 to D510 are recorded in the respective user data fields 62a.
Recorded between the resync patterns RS34 and RS35 are two bytes of data D511 and D512, four bytes of empty data FF, four bytes of cyclic redundancy check codes CRC1 to CRC4, and ten bytes of error correction codes Ea1 to Ee1 and Ea2 to Ee2. The four CRC codes CRC1 to CRC4 comprise the CRC field 62b.
The ECC fields 62c are provided among the resync patterns RS35 to RS39. Each ECC field 62c consists of fifteen one-byte error correction codes. Hence, sixty one-byte error correction codes Ea3 to Ee3, . . . , and Ea14 to Ee14 are recorded between the resync patterns RS35 and RS39. Ten one-byte error correction codes Ea15 to Ee15 and Ea16 to Ee16 are recorded after the last resync pattern RS39. Thus, eighty error correction codes Ea1 to Ee1, . . . , and Ea16 to Ee16 and five hundred and twelve data D1 to D512 are recorded in one sector.
The individual patterns, data and codes in each sector 60 are arranged in the direction of the arrow and the top-to-down direction in FIG. 3. In FIG. 3, one vertical line or column of data written in this order is called an "interleave". In this case, there are five interleaves. One interleave therefore consists of 120 bytes of data.
Error correction is carried out for each interleave. Sixteen error correction codes are assigned to each of the interleaves 1 to 5. For example, the error correction codes Ea1 to Ea16 are assigned to interleave 1 and the error correction codes Ed1 to Ed16 are assigned to interleave 4.
The Reed-Solomon code which exhibits a high correction performance is used for the error correction codes for each interleave, with one byte treated as an element of one code word. It is possible to detect which byte in a single interleave is in error and how it is in error, up to eight bytes (eight pieces of data). The Reed-Solomon code on an optical disk treats each element of the code word as an element of a Galois field in byte correction.
The disk interface 53 detects each data in the ID area 61 in a sector 60 to determine if the sector 60 is the target one. The disk interface 53 reads the sync patterns SB1-SB3 and resync patterns RS1-RS39 in the data area 62. When the reading of the sync patterns SB1-SB3 and resync patterns RS1-RS39 is successful, the disk interface 53 sends subsequently read data D.sub.R regarding individual data and codes to the speed matching buffer 57 and the error correcting unit 55. The disk interface 53 sends write data D.sub.W to be recorded on an optical disk to the drive head in accordance with the aforementioned format.
The speed matching buffer 57 is a first-in first-out (FIFO) type buffer memory. The FIFO buffer 57 has sixteen address areas with a capacity of one byte per address. The FIFO buffer 57 receives data from the disk interface 53 byte by byte and sequentially outputs the data to the data transfer controller 56. The data transfer controller 56 receives data from the FIFO buffer 57 and stores the data in a buffer memory 59.
The data and individual codes in one sector 60, which are supplied to the FIFO buffer 57 from the disk interface 53, are also sent to the error correcting unit 55. When receiving one sector of data and codes, the error correcting unit 55 performs an error correction operation for each interleave. The error correction operation for each interleave acquires a syndrome from the entire code word of 120 bytes which constitutes that interleave. Based on this syndrome, it is detected which byte in the interleave is in error and how it is in error. When a byte is in error, the internal processor 52 sends a replacement value to the data transfer controller 56. Based on the replacement value, the data transfer controller 56 corrects the erroneous content of the data and codes which have been previously stored in the buffer memory 59.
Thereafter, the error-corrected data in the buffer memory 59 is read out to the data transfer controller 56 and is then transferred via the host interface 54 to an external higher rank external unit (not shown).
The data transfer controller 56 also receives write data D.sub.W from the external higher rank unit via the host interface 54 and temporarily stores the write data D.sub.W in the buffer memory 59. Thereafter, the data transfer controller 56 reads the write data D.sub.W from the buffer memory 59 and sends the write data D.sub.W to the disk interface 53 via the FIFO buffer 57.
This signal processing unit 50 has the FIFO buffer 57 provided between the disk interface 53 and the data transfer controller 56. Even when the data transfer controller 56 performs data transfer with an external higher rank unit using the buffer memory 59, the disk interface 53 can read the read data D.sub.R from the optical disk and can write the data read in the FIFO buffer 57. The instance the data transfer process with the external higher rank unit is completed, therefore, the data transfer controller 56 can read data from the FIFO buffer 57 and can transfer it to the buffer memory 59. This allows the signal processing unit 50 to immediately execute the next signal processing operation, thus quickening the signal processing by the signal processing unit 50.
When reading the sync patterns SB1-SB3 fails, the disk interface 53 determines that the detection has failed. Then, the disk interface 53 outputs dummy data D.sub.D to the FIFO buffer 57. The dummy data D.sub.D corresponds in number (fifteen) to the data D1 to D15 in the user data field 62a located between the sync patterns SB1-SB3 and the resync pattern RS1. Each dummy data D.sub.D consists of one byte whose bits are all "0". The dummy data D.sub.D output to the FIFO buffer 57 is sequentially stored in the buffer memory 59 via the data transfer controller 56.
When reading the resync patterns RS1 to RS39 is successful, the disk interface 53 sequentially outputs the subsequent read data D.sub.R i.e., the data in the user data field 62a and the individual codes in the CRC field 62b and the ECC field 62c, to the FIFO buffer 57. The data transfer controller 56 reads the data and codes from the FIFO buffer 57 and stores the same in the buffer memory 59.
The dummy data D.sub.D, the data in the user data field 62a and the individual codes in the CRC field 62b and the ECC field 62c are also sent to the error correcting unit 55. Based on one sector of data and codes including this dummy data D.sub.D, the error correcting unit 55 executes an operation for error correction for each interleave. In this case, the error correcting unit 55 finds out how many of the whole dummy data D.sub.D are in error. The internal processor 52 sends a replacement value for each dummy data D.sub.D stored in the buffer memory 59 to the data transfer controller 56. Based on the replacement values, the data transfer controller 56 corrects the associated dummy data D.sub.D stored in the buffer memory 59. This error correction scheme is used in an optical disk accessing apparatus disclosed in Japanese Unexamined Patent Publication No. 1-124158.
FIG. 4 shows a timing chart for the signal processing unit 50 when reading the sync patterns SB1-SB3 has failed. When reading the sync patterns SB1-SB3 fails during a detection timing (detection window) T.sub.W1 for the sync patterns SB1-SB3, the disk interface 53 outputs dummy data D.sub.D. That is, when the detection timing (detection window) T.sub.W1 passes and after determining whether or not the reading of the sync patterns has failed, the disk interface 53 outputs the dummy data D.sub.D. After the detection timing (detection window) T.sub.W1 passes, therefore, the dummy data D.sub.D is written in the FIFO buffer 57 with a delay of time T.sub.D1. After a further delay of time T.sub.D2, the dummy data D.sub.D is read from the FIFO buffer 57.
However, the writing of the dummy data D.sub.D into the FIFO buffer 57 of the conventional signal processing unit 50 involves the following problems.
Due to cost and size reductions, the FIFO buffer 57 has a small capacity, which is generally sixteen (16) bytes. When fifteen (15) bytes of dummy data D.sub.D are written in the FIFO buffer 57, the remaining capacity is just one (1) byte. Therefore, when the dummy data D.sub.D is written in the FIFO buffer 57 with a delay of time T.sub.D1, a time T.sub.D3 from the beginning of the writing of the dummy data D.sub.D into the FIFO buffer 57 to the beginning of the writing of the data D16-D30 in the user data field 62a, (following the next resync pattern RS1 read out), becomes shorter. Consequently, the data D16-D30 cannot be written in the FIFO buffer 57 until there is sufficient available space in the FIFO buffer 57. Also, to complete the discussion of FIG. 4, T.sub.W2 is the detection timing (detection window) for the resync pattern RS1, and T.sub.D4 is the time from the beginning of the writing of the data D16-D30 to the beginning of the reading thereof.
Thus, when reading the sync patterns fails, it takes an inordinate amount of time to write data in the FIFO buffer 57.